信號發(fā)生器設(shè)計(jì)VHDL代碼Quartus仿真

名稱：信號發(fā)生器設(shè)計(jì)VHDL代碼Quartus仿真

軟件：Quartus

語言：VHDL

代碼功能：

信號發(fā)生器設(shè)計(jì)

信號發(fā)生器由波形選擇開關(guān)控制波形的輸出,分別能輸出正弦波、方波和三角波三種波形,波形的周期為2秒(由40M有源晶振分頻控制)。

考慮程序的容量,每種波形在一個周期內(nèi)均取16個取樣點(diǎn)，每個樣點(diǎn)數(shù)據(jù)是8位（數(shù)值范圍：00000000~1111111），要求將D/A變換前的8位二進(jìn)數(shù)據(jù)(以十進(jìn)制方式)輸出到數(shù)碼管動態(tài)演示出來。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計(jì)文檔：

1. 工程文件

2. 程序文件

3. 程序編譯

4. RTL圖

5. Testbench

6. 仿真圖

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
ENTITY?wave_generation?IS
???PORT?(
??????clk_in?????????:?IN?STD_LOGIC;--輸入時鐘40M
??????sys_rst?????????:?IN?STD_LOGIC;--高電平復(fù)位
??????
??????wave_select?????:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);--00方波;01-三角波;10-正弦波
HEX2?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--數(shù)碼管
HEX1?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--數(shù)碼管
HEX0?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--數(shù)碼管
???);
END?wave_generation;
ARCHITECTURE?behaviour?OF?wave_generation?IS
--分頻模塊，40m分頻到8hz
COMPONENT?div?IS
???PORT?(
?????????clk_in?:?IN?STD_LOGIC;
?????????clk_out?:?OUT?STD_LOGIC
???);
END?COMPONENT;
???--波形發(fā)生模塊
COMPONENT?carrier_wave?IS
??????PORT?(
?????????clk?????????????:?IN?STD_LOGIC;
?????????rst?????????????:?IN?STD_LOGIC;
?????????triangular_wave?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????square_wave?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????sin_wave????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
--3選1模塊，00方波;01-三角波;10-正弦波;wave_select控制3選1
COMPONENT?MUX_41?IS
???PORT?(
?????????triangular_wave?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????square_wave?????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????sin_wave????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????wave_select?????:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);--00方波;01-三角波;10-正弦波
?????????wave_data???????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--波形輸出
???);
END?COMPONENT;
--數(shù)碼管顯示模塊
COMPONENT?display?IS
???PORT?(
??????wave????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--波形
HEX2?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--數(shù)碼管
HEX1?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--數(shù)碼管
HEX0?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--數(shù)碼管
???);
END?COMPONENT;
???SIGNAL?sys_clk?:?STD_LOGIC;
???SIGNAL?triangular_wave?:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?square_wave?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?sin_wave????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
SIGNAL?wave_data???????:?STD_LOGIC_VECTOR(7?DOWNTO?0);--波形輸出
BEGIN
--分頻模塊，40m分頻到8hz
div_U?:?div
???PORT?MAP(
?????????clk_in=>clk_in,
?????????clk_out=>sys_clk
???);
???
???--波形產(chǎn)生模塊
???carrier_wave_ge?:?carrier_wave
??????PORT?MAP?(
?????????clk??????????????=>?sys_clk,
?????????rst??????????????=>?sys_rst,
?????????triangular_wave??=>?triangular_wave,
?????????square_wave??????=>?square_wave,
?????????sin_wave?????????=>?sin_wave
??????);

點(diǎn)擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=565