電子定時器洗衣機控制Verilog代碼Quartus 睿智FPGA開發(fā)板

名稱：電子定時器洗衣機控制Verilog代碼Quartus? ?睿智FPGA開發(fā)板

軟件：Quartus

語言：Verilog

代碼功能：

1.設計一個電子定時器,控制洗衣機作如下運轉:定時啟動，正轉20秒，暫停10秒，反轉20秒，暫停10秒，定時未到回到“正轉20秒暫停10秒.....

2.若定時到，則停機發(fā)出音響信號。

3.用兩個數碼管顯示洗滌的預置時間（分鐘數),按倒計時方式對洗滌過程作計時顯示，直到時間到停機;洗滌過程由“開始”。

4.三只LED燈表示“正轉”、“反轉”，“暫?！比齻€狀態(tài)。

定時器定時,數碼管顯示預置分鐘數,led燈顯示三個狀態(tài),定時結束發(fā)出音響信號。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

本代碼已在?睿智FPGA開發(fā)板驗證，?睿智FPGA開發(fā)板如下，其他開發(fā)板可以修改管腳適配：

演示視頻：

設計文檔：

1. 工程文件

2. 程序文件

3. 程序編譯

4. 仿真圖

部分代碼展示:

module?washing_machine(clk_in,?dataout,en,reset_n,?start_key,?led,?end_beep);
???input????????clk_in;//50MHz
???input????????reset_n;//復位按下低電平
???input????????start_key;//啟動按下低電平
???
???output?[2:0]?led;//正反轉燈???
???output???????end_beep;//結束報警
???
output[7:0]?dataout;//數碼管段選
output[3:0]?en;//COM使能輸出
???
???
???reg?[1:0]????state;
???reg?[2:0]????led;???
???reg?[7:0]????washing_time;???
???reg??????????end_beep_buf;
???reg?[7:0]????second_cnt;
???reg??????????min_en;???
???reg??????????second_en_1s;
???reg?[31:0]????second_div_cnt;
???
reg?[31:0]?beep_cnt=32'd0;???
???always?@(posedge?clk_in?or?negedge?reset_n)
if(!reset_n)
state<=2'b00;//空閑狀態(tài)
else
?????????case?(state)
????????????2'b00?://空閑狀態(tài)
???????????????if?(start_key?==?1'b0)
??????????????????state?<=?2'b01;
???????????????else
??????????????????state?<=?2'b00;
????????????2'b01?://倒計時狀態(tài)
???????????????if?(washing_time?>?8'b00000000)
??????????????????state?<=?2'b01;
???????????????else
??????????????????state?<=?2'b10;
????????????2'b10?://結束
state?<=?2'b10;
????????????default?:
???????????????state?<=?2'b00;
?????????endcase
?
???always?@(posedge?clk_in)??????
??????begin
?????????if?(state?==?2'b10)//結束計數
????????????beep_cnt?<=beep_cnt+?1'b1;
??????end???
???
???always?@(posedge?clk_in)??????
??????begin
?????????if?(state?==?2'b10)//結束
????????????end_beep_buf?<=?1'b1;
?????????else
????????????end_beep_buf?<=?1'b0;
??????end
??reg?[31:0]?beepclk_cnt=32'd0;
??reg?beepclk=0;
???always?@(posedge?clk_in)??????
??????begin
if(beepclk_cnt>=32'd25_000)begin//仿真時將25_000改小為10
beepclk_cnt<=0;
beepclk<=~beepclk;
end
else?begin
beepclk_cnt<=beepclk_cnt+1;
beepclk<=beepclk;
end
??????end
??
???assign?end_beep?=?end_beep_buf?&?beepclk;
???
???
???always?@(posedge?clk_in)
if(state!=2'b01)//非倒計時狀態(tài)清零
begin
????????????second_div_cnt?<=?32'd0;
????????????second_en_1s?<=?1'b0;
end
else//倒計時狀態(tài)計時
??????begin
?????????if?(second_div_cnt?>=?32'd50_000_000)//50_000_000--50M計數50000000為1s，仿真將計數器改小為50
?????????begin
????????????second_div_cnt?<=?32'd0;
????????????second_en_1s?<=?1'b1;//50MHz分頻為1Hz
?????????end
?????????else
?????????begin
????????????second_div_cnt?<=?second_div_cnt?+?32'd1;
????????????second_en_1s?<=?1'b0;
?????????end
??????end
???
???always?@(posedge?clk_in)?????
??????begin
?????????if?(state!=2'b01)//非倒計時狀態(tài)清零
????????????second_cnt?<=?8'b00000000;
?????????else?if?(second_en_1s?==?1'b1)//倒計時狀態(tài)計時
?????????begin
????????????if?(second_cnt?>=?8'd59)//59s
???????????????second_cnt?<=?8'd0;
????????????else
???????????????second_cnt?<=?second_cnt?+?8'd1;
?????????end
?????????else
????????????second_cnt?<=?second_cnt;
??????end
??
???always?@(posedge?clk_in)
??????
??????begin
?????????if?(second_en_1s?==?1'b1?&&?second_cnt?==?8'd59)
????????????min_en?<=?1'b1;//分鐘信號
?????????else
????????????min_en?<=?1'b0;
??????end
???
???
???always?@(posedge?clk_in)?????
??????begin
?????????if?(state?==?2'b00)
????????????washing_time?<=?8'd5;//默認5分鐘
?????????else?if?(min_en?==?1'b1)//分鐘信號
?????????begin
????????????if?(washing_time?>?8'd0)
???????????????washing_time?<=?washing_time?-?8'd1;//倒計時
????????????else
???????????????washing_time?<=?8'd0;
?????????end
?????????else
????????????washing_time?<=?washing_time;
??????end

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=575