名稱:單窗口排隊機電路設(shè)計VHDL代碼Quartus仿真
軟件:Quartus
語言:VHDL
代碼功能:
單窗口排隊機電路設(shè)計
在EDA平臺下使用VDL語言為工具,設(shè)計單窗口排隊機電路,給每個新加入排隊人員編號,并計算隊伍長度。
要求:
1.進入隊伍和離開隊伍為外界輸入信號,當(dāng)前服務(wù)號碼和當(dāng)前隊伍長度各由兩個數(shù)碼管顯示;
2.隊伍長度初始化后為0,隊伍編號由1開始遞增并輸出;
3.隊伍長度達到99后,若又有新加入人員,則輸出溢出報警;
4.每個人員完成業(yè)務(wù)后由業(yè)務(wù)員點擊完成,對該隊伍長度進行刷新。
FPGA代碼Verilog/VHDL代碼資源下載:www.hdlcode.com
演示視頻:
設(shè)計文檔:
1. 工程文件
2. 程序文件
3. 程序編譯
4. RTL圖
5. Testbench
6. 仿真圖
整體仿真圖
分頻模塊
控制模塊
顯示模塊
部分代碼展示:
LIBRARY?ieee; ???USE?ieee.std_logic_1164.all; --排隊設(shè)計 ENTITY?line?IS ???PORT?( ??????clk_in????:?IN?STD_LOGIC;--50MHz ??????reset_n???:?IN?STD_LOGIC;--復(fù)位 ??????in_line???:?IN?STD_LOGIC;--進隊 ??????out_line??:?IN?STD_LOGIC;--出隊 alarm_led?????:?OUT?STD_LOGIC;????--溢出 ??????dig_led???:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);--數(shù)碼管位選 ??????seg_led???:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--數(shù)碼管段選 ???); END?line; ARCHITECTURE?behave?OF?line?IS --50MHz分頻到1KHz ???COMPONENT?divider?IS ??????PORT?( ?????????clk_in????:?IN?STD_LOGIC;--50MHz ?????????clk_1K????:?OUT?STD_LOGIC--分頻得到1Khz ??????); ???END?COMPONENT; ???--顯示模塊 ???COMPONENT?display?IS ??????PORT?( ?????????clk???????:?IN?STD_LOGIC; ?????????current_num?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--當(dāng)前號碼 ?????????long_num??:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--隊長 ?????????dig_led???:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);--數(shù)碼管位選 ?????????seg_led???:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--數(shù)碼管段選 ??????); ???END?COMPONENT; ??? ???--排隊控制模塊 ???COMPONENT?line_ctrl?IS ??????PORT?( ?????????clk???????:?IN?STD_LOGIC;--1KHz ?????????reset_n???:?IN?STD_LOGIC;--復(fù)位 ?????????in_line???:?IN?STD_LOGIC;--進隊 ?????????out_line??:?IN?STD_LOGIC;--出隊 alarm_led?????:?OUT?STD_LOGIC; ?????????current_num?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--當(dāng)前號碼 ?????????long_num??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--隊長 ??????); ???END?COMPONENT; ??? ???SIGNAL?clk_1K????????:?STD_LOGIC; ??? ???SIGNAL?current_num???:?STD_LOGIC_VECTOR(7?DOWNTO?0);--當(dāng)前號碼 ???SIGNAL?long_num??????:?STD_LOGIC_VECTOR(7?DOWNTO?0);--隊長 ???SIGNAL?dig_led_buf?:?STD_LOGIC_VECTOR(3?DOWNTO?0); ???SIGNAL?seg_led_buf?:?STD_LOGIC_VECTOR(7?DOWNTO?0); BEGIN ???dig_led?<=?dig_led_buf; ???seg_led?<=?seg_led_buf; ??? ???--50MHz分頻到1KHz ???i_divider?:?divider ??????PORT?MAP?( ?????????clk_in??=>?clk_in,--50MHz ?????????clk_1K??=>?clk_1K--分頻得到1Khz ??????); ??? ???--排隊控制模塊 ???i_line_ctrl?:?line_ctrl ??????PORT?MAP?( ?????????clk??????????=>?clk_1K,--1KHz ?????????reset_n??????=>?reset_n,--復(fù)位 ?????????in_line??????=>?in_line,--進隊 ?????????out_line?????=>?out_line,--出隊 alarm_led??=>?alarm_led,--溢出報警 ?????????current_num??=>?current_num,--當(dāng)前號碼 ?????????long_num?????=>?long_num--隊長 ??????);
點擊鏈接獲取代碼文件:http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=582